1. Field of the Invention
This disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a double gate field effect transistor formed on a bulk substrate and a method of manufacturing the same.
2. Description of the Related Art
As the integration density of a semiconductor device increases, the size of a metal-oxide-semiconductor field effect transistor (MOSFET) is miniaturized. For a semiconductor device having a planarized transistor, the miniaturization of a transistor corresponds to a reduction in a channel length of the transistor, thereby improving the performance characteristics, such as an operating speed, of the device.
However, a few problems associated with a reduction of channel length below 100 nm are observed in a conventional MOSFET that includes a planarized transistor. An exemplary problem in this respect is the short distance between a source region and a drain region in the MOSFET. If the source region is too close to the drain region, they interfere with each other and affect the channel region. To avoid this problem, the concentration degree of a dopant should be increased. As a result, a device characteristic, i.e., an active switching function, which controls the operation of the transistor by controlling the gate voltage of the MOSFET is seriously degraded. This phenomenon is called a short channel effect (SCE). The SCE could degrade the electrical characteristics of the MOSFET, such as instability of sub-threshold voltage.
As a solution to solve the SCE problem in the MOSFET, a double gate field effect transistor has been proposed. The double gate field effect transistor has a non-planarized channel structure, and two gates are formed on both faces of the non-planarized channel. That is, the double gate field effect transistor has an advantage of an improved channel control capability because the channel is controlled by the two gates, thereby reducing the SCE problem. Also, when the double gate field effect transistor is in an “on” state by using the two gates, two inversion layers will be formed resulting in more current flowing through the channel.
An example of a fin-type field effect transistor (FinFET) is depicted in the papers “A Folded-channel MOSFET for Deepsubtenth Micron Era,” 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034, by Hasimoto et al., and “Sub 50-nm FinFET: PMOS,” 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 by Heang et al., which are hereby incorporated by reference. Referring to the above disclosures, the channel of FinFET is firstly formed on a substrate, and then a source region and drain region of FinFET are formed by using a conventional silicon deposition process.
U.S. Pat. No. 6,413,802 to Hu et. al. discloses a FinFET structure and a method of manufacturing the FinFET, which is formed on a solid silicon epitaxy layer deposited on a silicon on insulator (SOI) substrate or a bulk silicon substrate. The FinFET structure includes a fin as a channel formed vertically to an insulating film, and gates formed on both side surface of the fin. This FinFET structure has an advantage in that a conventional technique for manufacturing a planarized transistor can be applied to form the FinFET using a SOI substrate. Also, the structure has a superior electrical characteristic because the two gates are self aligned not only to each other but also to the source and drain regions. However, this method has some drawbacks since it requires high cost and a long process time for forming the solid epitaxy layer. Also, patterning the channel and source and drain regions to a desired shape is not easy.
Embodiments of the invention address these and other disadvantages of the conventional art.